Rate resolver which accepts an angular rate input and produces a sinusoidal output

ABSTRACT

THE DISCLOSURE CONCERNS AN ELECTRONIC RATE RESOLVER OF UNUSUALLY ADVANTAGEOUS CONSTRUCTION AND FOOLPROOF MODE OF OPERATION AND WHICH ACCEPTS INPUT REPRESENTATIVE OF AN ANGULAR RATE D$/DT AND PRODUCES SINCE $ AND COSINE $ SINUSOIDAL OUTPUT.

United States Patent inventor Gilbert R. Grado 17611 Orange Tree Lane. Tu stin. Calif. 92680 App] No 800,874

Filed Feb. 20, 1969 Patented June 28, 1971 RATE RESOLVER WHICH ACCEPTS AN ANGULAR RATE INPUT AND PRODUCES A References Cited UNITED STATES PATENTS Longerich lngwerson et a1 Brackel l-lerndon Faxen et a1. Dolan..

Schwartzenberg et a1. Schmid Primary Examiner-Malcolm A. Morrison Assistant ExaminerJoseph F. Ruggiero Au0rneyWhite and Haefliger ABSTRACT: The disclosure concerns an electronic rate resolver of unusually advantageous construction and foolproof mode of operation and which accepts input representative of an angular rate d 1 ldt and produces sine (I and cosine D sinusoidal output.

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RATE RESDLVER WHICH ACCEPTS AN ANGULAR RATE INPUT AND PRODUCES A SINUSOIDAL OUTPUT BACKGROUND OF THE INVENTION This invention relates generally to computing equipment, and more specifically concerns electronic rate resolvers .for use in such equipment.

Rate resolvers are useful in computing systems to provide one or more outputs that depend upon one of more inputs. For example, the simulation of three dimensional, six degree of freedom systems usually requires the use of accurate coordinate transformation so that rectangular-to-polar and polarto-rectangular conversions may be effected with a high degree of precision and reliability.

Present resolvers suffer from certain disadvantages, among which are undesirable complexity as well as ambiguities at switching points. For example, in a typical problem in simulation, the input angular rate (d ll/d!) can be a randomly varying signal, and a logic signal is developed when (I has reached 17/2 or --1r/2 radians to toggle a flip-flop controlling the inputs to sine or cosine generators. It is found that ambiguity can result when d I /dt reverses direction immediately after the flip-flop has toggled at the switching point, the circuit then being unable to reverse direction.

SUMMARY OF THE INVENTION It is a major object of this invention to provide an unusually effective and reliable rate resolver characterized by the following features and advantages: the rate resolver accepts an input representative of an angular rate dQ/dt and produces sine 1 and cosine I sinusoid generation outputs the sinusoid functions appear as a continuous wave, even though the angle I passes through more than one cycle; and the rate resolver accepts an extremely wide range of rate inputs. Whereas conventional electronic rate resolvers can yield erroneous results under some input signals, the rate resolver mentioned here offers completely foolproof operation for all input signals.

Basically, the invention is embodied in a resolver that includes sine and cosine 1 generators; and means responsive to d l /dt inputs of opposite polarity and to a reference voltage to supply to the generators l and 1r/2+/ I inputs as l varies through mr/Z radians, where n is greater than 1, thereby to form a sinusoid function over the angular range. As will appear, the supply means may advantageously include a d I /dt integrator, and a first switch to control transmission to the integrator of d i /dt signals of opposite polarity, logic circuitry typically effecting operation of the first switch when 1 reaches 1r/2 radians thereby to reverse the polarity of the d D/dt input to the integrator.

Further, the supply means referred to may advantageously include multiple channels connected in parallel between the integrator and the cosine generator, one channel to supply q input to the generator, a second channel to supply 1r/2 input to the cosine generator and a third channel to supply 24 input to the cosine generator when I lies between the limits to n radians. As will appear, the supply means may also include a second switch operatively connected in a fourth channel to control transmission to the cosine generator of an input equivalent to the sum of the inputs of channels one, two and three multiplied by a factor of 2, logic circuitry efi'ecting operation of the second switch when I reaches the 11/2 and 1r/2 limits.

A further aspect of the invention concerns the provision of logic circuitry comprising a flip-flop (or equivalent) the out puts of which are connected to the mentioned switches, and multiple comparators to monitor the polarity of D and the arrival of l at the limits of 11/2 and 1r/2, and gates operatively connected between the comparators and flip-flop, as will be described. Further, an additional comparator may be provided, with unusual advantage, to monitor d I /dt and to provide certain output logic signals when dQ/dt is within a range corresponding to a predetermined small percentage of full scale, together with an auxiliary gate to operate the flip-flop in response to reception of those certain output logic signals and the output of that comparator monitoring the arrival of I at the limits 1r/2 and 1r/2, all for the purpose of preventing ambiguity development, as will appear.

These as well as other objects and advantages of the invention, as well as the details of an illustrative embodiment, will be more fully understood from the following detailed description of the drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one preferred form of the rate resolver;

FIG. 2 is a block diagram of the control logic for the FIG. 1 resolver;

FIG. 3 illustrates sine and cosine output wave forms as related to the generated angle; and

FIG. 4 is a vector diagram.

DESCRIPTION OF PREFERRED EMBODIMENTS FIG. 1 illustrates, generally, sine D and cosine I generators l0 and 11 incorporating amplifiers l2 and 13 and feedback circuitry in blocks 14 and 15. The latter represent networks of diodes and resistors such as will effect production of the I sinusoid functions at the outputs I6 and 17 of the generators, as for example over the I range :rr/Z radians or The circuitry to the left of the generators may be characterized as one form of means responsive to dQ/dt (i.e. rate of change of I inputs of opposite polarity, and to reference voltage, to supply to the generators I and 1r/2- inputs, as 1 varies through mr/2 radians where n is greater than I, defining a wide range of I variance.

The supply means referred to typically includes a d l ldt integrator I8 and a first switch DAI to control transmission to the integrator of d l /dt signals of opposite polarity. For example, dQ/dt input may be supplied to the integrator on channel 19, whereas when switch DA! is closed, 2dI /dt input is supplied to the integrator via channel 20 (which includes inverting amplifier 21), whereby the net input to the integrator is the signal a'Q/dt. When switch DAl is open, only +d /dt reaches the integrator. As will appear, the logic control of switch DA] is such that the output of amplifier 21 is as follows:

d l /dt for 1r/2 1 -1r/2 (2) where 1 is an angle within the bounds of in radians, as for example indicated in FIG. 3.

The output I of the integrator 18 is as follows:

The illustrated supply means may also be considered to include multiple channels connected in parallel between the integrator 18 and the cosine generator; for example, one such channel 22 supplies I input to the generator 11, a second channel 23 supplies rr/2 input to that generator, and a third channel 240 supplies +2I input to that actuator when 1 lies between the limits 0 and 11'. A fourth channel 24b supplies an inverted signal equivalent to twice the sum of the other cosine generator inputs when 1 lies between 1r/2 and 11', and the limits rr/2 and 1r. The effect of channel 24b is to reverse the polarity of the cosine function when '1 lies between the limits 17/2 and 1r, and the limits 1r/2 and -1r. Another channel 25 supplies input to the sine generator 10, as shown.

Channels 24a and 24b contain resistors R R,, R, R R and R,;, as indicated, with the signal at Y in 240 equal to:

The output if from channel Ma is supplied as l varies in all four quadrants, whereas the output Z is supplied only as l varies in quadrants Ill and Ill, due to the switching action of DA2 in channel Zdb, as will be described.

The input to amplifier 13 in Quadrant II is: (fir/2l 2Y+AYx[rr/2(1ral ll )]+2(11-)+2(1r/2+ l )=1r/2-Hl l 3) The output of amplifier 13 is the inverted sine function of the input angle. Therefore, its output is sine (-1r/2), or cosine l In Quadrant III the input to amplifier 113 is: (1r/2 l Y-l-ZA x(1r/2+11-l-)+2 l +2(1r/2 l )=-1r/2+ l (14) The output of amplifier l3 in Quadrant III is equal to the sine (11/2+) or cosine l The net result is that the sine and cosine functions appear to be continuous as determined by the input angular rate, even though the generated angle l is restricted to the bounds of in radians. In effect, in FIG. 4, a rotating vector will operate only in Quadrants l and IV, but the outputs indicate operation in all four quadrants.

Another aspect of the invention concerns the provision of logic circuitry to effect operation of switch DAl when reaches 'rr/2 radians, thereby to reverse the polarity of the d l ldt input to the integrator l8; and logic circuitry to effect operation of switch DA2 when reaches the 11/2 and 1r/2 limits.'As will be seen, the logic circuitry may advantageously include a flip-flop having outputs operatively connected to the switches DAl and DA2, and multiple comparators monitoring certain parameters and controlling the state of the flip-flop via gates.

As seen in FIGS. l and 2, a first comparator 29 is connected with the il output of the integrator 18 via resistor, diode and. amplifier network 30, and monitors the polarity of db. Thus, the logic signal output of the comparator (75 is true if I is positive, and false, if Q is negative. The complementary output (A) is true when 4 is negative and false if 1 is positive. A second comparator 31 is connected via the illustrated resistor, diode and amplifier network 32 with the i output of the integrator and with a reference voltage source 33, and monitors the arrival of Q at the limits 1r/2 and 1r/2. For example, the logic signal output of the comparator 31 @will go true upon arrival of the integrator output voltage at +50 volts or 50 volts in the case where those voltages are selected to represent 1r/2 and -rr/2 respectively, It is understood that other voltages may be used. In this regard, switch DA2 is closed when I is between 1r/2 and 11', and between 1r/2 and -11, and the circuit of channel 24b, including amplifier 34, then drives the output of the cosine generator in the negative direction.

A third or auxiliary comparator 35 is provided to monitor the polarity of (NP/d! for furnishing certain output logic signals. The logic output R is true if the rate is positive, and false if the rate is negative. The logic output if is true for negative rates and false for positive rates. The comparator has the feature that both logic outputs are false for d l /dt input levels less than 0.0l percent of full scale; for a l-volt analog computer system, comparator 35 would have its output logic signals false for rate inputs less than millivolts. This compensates for the effects of integrator drift, and comparator imperfection. For example, if the comparator indicates a positive d l /dt rate and the integrator drifts in the direction caused by negative rate, the resolver could go into a lockup condition, in the absence of such compensation. The 10 millivolt deadzone assures that the comparator and integrator will always be in agreement, as further described below.

Referring to FIG. 2, the four NAND gates 40, ill, 42 and 43 are connected at 44 and 415 to directly set or reset the flip-flop, depending on the logic input to the gates, such inputs indicated as A, A, R, R C and (T For example, if the flip-flop is initially reset, and then if the angle reaches 1r/2 radians (G goes true), the angle is positive (A is true), and the rate is positive (R is true), the result is that gate 42 will set the flip-flop. With the flip-flop set, the DA switches (DAl and DA2) will close, causing the input to the integrator 18 to reverse and switching the polarity of the cosine function. Gate 43 will set the flip-flop if the rate is negative, the angle is negative, and the angle has reached -1r/2 radians. Gate 411 will reset the flipflop if the rate is positive, the angle negative, and the angle has reached -1r/2 radians. Gate 40 will reset the flip-flop if the rate is negative, the angle is positive, and the angle has reached +11 /2 radians.

An auxiliary gate 50 operates the flip-flop 60 in response to output signals R, iand C, as indicated in FIG. 2. For example, for signals less than 10 millivolts gate 50 is used to toggle the flip-flop if both R and Rare false, the angle has reached :1r/2 radians (Gis true and C is false), and a delay circuit 511 is not inhibiting gate 50. The change of state of gate 50 will automatically activate the delay circuit, as via line 52. The delay is inversely proportional to the time derivative of the angle, and typically, the delay ranges from 5 milliseconds to 0.5 seconds to cover the range of integrating time constants from 10 to 0.001 seconds. The use of this technique for small rates is greatly simplified over the conventional rate resolver, because the range of rate inputs is restricted to the bounds of 0.01 percent of full scale, typically.

The deadzone of the comparator can be set to other values, depending on the drift characteristics of the integrator and offset characteristics of the comparator. Rate circuit 53 consists of a differentiator which generates a voltage proportional to the absolute value of the angular rate.

It should be observed that whenever the rate input, (d l /dt) is greater than 0.01 percent, the rate comparator 35 generates a logic signal (either IR is true, or R is true) that controls the inputs to the four gates (40, ll, 42, 43) in a straightforward manner. The flip-flop 50 has to react immediately to the requests of the gates, and the direction that the flip-flop is going is the right way because we know where we are (the angle comparator), where we are going (the rate comparator), and the need to change states (the 1r/2 limit comparator). In the very small area (0.01 percent) where the input rate is not well established, the resolver has the advantage that even if the rate changes direction, it cannot go very far, because as it exceeds 0.0] percent of the full scale signal, the direct circuits will take over again. Within the realm of the input signal staying within 0.01 percent, the flip-flop will toggle. The use of the rate circuit and the delay circuit assures that the resolver will operate without error in this small region. Outside of this range (which is 9,999 parts out of 10,000) the operation is completely foolproof.

In summary, the rate resolver described herein offers completely foolproof operation for all combinations of input angular rates. The resolver has no restrictions on the number of revolutions through which the angle may rotate. A logic signal is available DA to drive a counter, as at 54, to keep track of the number of revolutions. Being an all-electronic device, it is not restricted in speed except for the error generated in the amplifiers and associated networks. The ohmic values of the resistors in FIG. 1 are representative only, and other values may be used so long as the mode of operation remains.

I claim:

1. In a resolver,

A. sine l and cosine I generators and B. means responsive to d'l /dt inputs of opposite polarity and to reference voltage to supply to the generators l and 'rr/2 inputs as 1 varies through m l /2 radians where n is greater than l said means including a d l ldr integrator.

a first switch to control transmission t9 the integratgg Qf d l dt siggals of opposite polarity, logic circuitry to effect limits 1rl2 and 1r, and the limits rrZ2 and and logic circuitry to efi'ect operation of said second switch when Q reaches said 112 and #117 limits,

2. The resolver of claim 1 wherein said logic circuitry includes a flip-flop the outputs of which are operatively connected to said switches, multiple comparators to monitor the polarity of I and the arrival of 1 at the limits 1r/2 and -1r/2, and gates operatively connected between said comparators and flip-flop.

3. The resolver of claim 2 wherein said logic circuitry includes an additional comparator to monitor d i /dt and providing output logic signals indicative of the polarity of the input rate dQ/dt for controlling the status of said switches.

4. The resolver of claim 3 wherein said comparator generates certain output logic signals when d D/dt is within a range corresponding to a predetermined small percentage of full scale and said logic circuitry includes an auxiliary gate to operate the flip-flop in response to reception of said certain output signals and the output of the comparator monitoring the arrival of D at the limits 1r/2 and -rr/2.

5. The resolver of claim 3 including circuitry to inhibit said auxiliary gate when d I /dt is outside said range and to enable said gate when dQ/dt is within said range. 

